High density interconnects is an important design in the fabrication of printed circuit boards with microvias and through-holes. Miniaturization of these devices relies on a combination of thinner core materials, reduced line widths and smaller diameter through-holes and blind vias. The diameters of the through-holes range from 75 μm to 200 μm. Filling the through-holes by copper plating has become more and more difficult with higher aspect ratios. This results in larger voids and deeper dimples. Another problem with through-hole filling is the way they tend to fill. Unlike vias which are closed at one end through-holes pass through a substrate and are open at two ends. Vias fill from bottom to top. In contrast, when through-holes are being filled with copper, the copper tends to begin to deposit on the walls at the center of the through-hole where it plugs at the center forming “butterfly wings” or two vias. The two vias fill to complete the deposition of the holes. Accordingly, the copper plating baths used to fill vias are not typically the same as are used to fill through-holes. Plating bath levelers and other bath additives are chosen to enable the right type of fill. If the right combination of additives is not chosen then the copper plating results in undesired conformal copper deposition.
Often the copper fails to completely fill the through-hole and both ends remain unfilled. An incomplete through-hole fill with copper deposit in the center with unfilled ends is sometimes referred to as “dog-boning”. The open spaces at the top and bottom of the holes are referred to as dimples. Entire dimple elimination during through-hole filling is rare and unpredictable. Dimple depth is perhaps the most commonly used metric for quantifying through-hole fill performance. Dimple requirements depend on through-hole diameter and thickness and it varies from one manufacturer to another. In addition to dimples, gaps or holes referred to as voids may form within a copper through-hole fill. Larger dimples affect further processing of the panel and larger voids affect device performance. An ideal process completely fills through-holes with a high degree of planarity, i.e., build up consistency, without voids to provide optimum reliability and electrical properties and at as low as possible a surface thickness for optimum line width and impedance control in an electrical device.
Another problem associated with through-hole filling is filling through-holes with electrolytic copper when the through-hole walls have a layer of flash copper. Typically substrates containing through-holes, such as printed circuit boards, are copper clad with a layer of electroless copper on a surface and on the walls of the through-holes. Electroless copper thickness is usually greater than 0.25 μm. Such electroless copper layers tend to oxidize. Often printed circuit boards are electrolessly plated with copper and stored for a period of time prior to further processing. Prolonged periods of exposure to air as well as general handling of the boards result in relatively rapid oxidation of the electroless copper layer. To address this problem the industry electroplates a layer of flash copper 2 μm to 5 μm thick on the surface of the electroless copper prior to storage to protect the electroless copper from oxidation. Also, the thicker flash copper layer allows for removal of any oxide formation during storage by conventional etching processes whereas such etching cannot be done on the thinner electroless copper without the danger of damaging or removing the electroless copper layer. Unfortunately, electrolytic copper flash adds to the difficulty of filling through-holes. Dimpling and void formation frequently occur when workers try to fill through-holes using electrolytic acid copper plating baths.
Accordingly, there is a need for a method to improve through-hole filling in substrates which have a flash copper layer.